As transistors shrink in size to allow higher density and lower power devices, the maximum voltage that transistors can withstand without damage also decrease. These transistors make up integrated circuits (ICs) and devices that are powered by low-voltage direct current (DC) power sources. For example, mobile devices containing these transistors may be powered by a rechargeable battery. Transistor technology often moves from one generation to the next at a faster rate than battery technology. Thus, there may be a mismatch between the maximum voltage that the transistor can withstand and the power source can provide. For example, a battery may output a voltage between 3.6 Volts and over 5 Volts, depending on the charge level of the battery. However, transistors may have a lower maximum voltage than the battery output. For example, a 5 Volt laterally-diffused metal-oxide-semiconductor (5V LDMOS) transistor may have safe operating areas of −3.6 Volts to +3.6 Volts for the gate-to-source voltage, −3.6 Volts to +5.5 Volts for the gate-to-drain voltage, −3.6 Volts to +3.6 Volts for the gate-to-base voltage, −0.6 Volts to +3.6 Volts for the base-to-source voltages, and −5.5 Volts to +0.6 Volts for the drain-to-base voltage. Some of these safe operating ranges are smaller than the maximum possible output voltage of the battery.
If the transistor receives a larger voltage than the maximum acceptable voltage for one of the operating areas, then the transistor may be irreparably damaged and cause the device containing the transistor to stop working. In particular, in the example described above, n-channel metal-oxide-semiconductor (NMOS) transistors with their source connected to ground cannot have their gate voltage pulled to the positive supply voltage provided by the power source. Additionally, in the example described above, p-channel metal-oxide-semiconductor (PMOS) transistors with their source connected to the positive supply voltage cannot have its gate pulled down to ground. Thus, for example, when the power supply voltage is between 3.6 Volts and 5.0 Volts, these metal-oxide-semiconductor transistors are unable to have their gates swing from positive to negative supply voltages, which most complementary metal-oxide-semiconductor (CMOS) circuits are designed for. In this situation, certain conventional commonly-used CMOS circuits, which include both PMOS and NMOS transistors, are unavailable for use in design of the device.
FIG. 1 is a circuit illustrating a prior art inverter. An inverter 100 includes a p-channel metal-oxide-semiconductor (PMOS) transistor 112 and an n-channel metal-oxide-semiconductor (NMOS) transistor 114 coupled together. The PMOS transistor 112 is also coupled to a positive supply voltage, Vdd, and the NMOS transistor 114 is also coupled to a negative supply voltage, Vss. An input provided to the inverter 100 at input node 102 is inverted at an output node 104. For example, an input ‘1’ value to the input node 102 will produce an output ‘0’ value at the output node 104.
FIG. 2 is a circuit illustrating a prior art level shifter. A level shifter 200 includes cross-coupled PMOS transistors 232 and 234 and NMOS transistors 212 and 214. The PMOS transistors 232 and 234 are also coupled to the positive supply voltage, Vdd, and the NMOS transistors 212 and 214 are also coupled to the negative supply voltage, Vss. An input to the level shifter 200 at input node 102A is inverted at input node 102B to provide a differential input to the level shifter 200. An output at the output nodes 104A and 104B is level shifted from the input provided at the input node 102A.
In each of the circuits of FIG. 1 and FIG. 2, the PMOS transistors 112, 232, and 234 have their source connected to the positive supply voltage, Vdd, and thus cannot have their gates pulled down to ground. Likewise, the NMOS transistors 114, 212, and 214 have their source connected to the negative supply voltage, Vss, and thus cannot have their gate voltage pulled up to the positive supply voltage.
In prior solutions, a level shifter was coupled to the gate of a transistor and the level shifter selected between a supply voltage and a cascoded voltage to limit operation of the transistor outside of safe operating areas. However, when the threshold voltage of the transistor increases, due to manufacturing variation or design, or when the battery is discharged and the supply voltage is low, the circuit's performance degrades. In particular, the level shifter operates in sub-threshold conduction, creating large output impedance. The level shifter then loses drive strength and becomes susceptible to noise, and the transition time is increased. As the power supply voltage drops in these circumstances, control of the level shifters is lost and it becomes impossible to safely turn off circuit blocks with power switches.
Shortcomings mentioned here are only representative and are included simply to highlight that a need exists for improved transistor-based devices, particularly for consumer-level devices. Embodiments described here address certain shortcomings but not necessarily each and every one described here or known in the art.